ASIC Design and Implementation of SPST in FIR Filter

Spurious Power Suppression Technique (SPST) is a technique used for reducing the power in VLSI circuits by neglecting the unwanted or spurious signals present at the input. The proposed SPST separates the target design into two parts, i.e.,the most significant part and least significant part (MSP and LSP) and turns off the MSP when it does not affect the computational result to save power. This technique dramatically reduces the power dissipation in multimedia/DSP application design examples, i.e., versatile multimedia functional unit (VMFU) and FIR Filters. In this project we specifically reduce the power consumed by the multipliers present in FIR Filters using Modified Booth Encoding Algorithm combined with SPST. It also adopts the optimization of number of cells present in the design. The proposed design of SPST in FIR Filter will be designed using Verilog HDL and synthesized, implemented using Cadence ASIC Tools.